On-Premise AI. Hardware-Accelerated. Fully Secure.
Deploy sovereign AI infrastructure on your premises with our proprietary FPGA-based solutions. Full data control, real-time inferencing, and confidential computing -- built for enterprises that demand zero-compromise security.
Trusted across regulated industries
Products
A growing portfolio for secure, high-throughput compute
Our product lines are delivered as silicon-ready IP — deployable on FPGA or licensable for ASIC integration at 2 GHz and above.
HP-Secure 1.0
A CC-312-class edge security engine with hardware multi-tenancy built in. A single fixed-function block partitions into independent, hardware-isolated tenants — each with its own keys and sessions — running a modern crypto suite proven on silicon today.
- Hardware-isolated multi-tenancy
- Modern suite: AES-XTS, SHA-2/3, ChaCha20-Poly1305
- Proven on FPGA, ASIC-ready
HP-Secure 3.0
A Structera-class inline confidential-compute engine, licensed as RTL — line-rate encryption, authentication, key management and compression for CXL/PCIe fabrics, memory expanders and data movers, with hardware-enforced multi-tenant isolation. One configurable RTL, not a fixed part.
- Inline security + LZ4 compression at line rate
- SR-IOV multi-tenant isolation
- Licensable RTL — one config, many SKUs
HP-VPU (NPU)
Inference at the edge. A scalable RISC-V Vector (RVV-1.0) processor and a dense INT8/INT4 GEMM engine on one substrate — two engines sharing one register file, built for LLM and ML inference. Fully quantized, RISC-V-native, and verified byte-exact against open standards.
- RVV-1.0 vector core + LLM-inference NPU
- Fully quantized (INT8 / INT4), no FP datapath
- Scales by replication; proven on FPGA
HP-CORE
A server-class RISC-V core family. The midcore is a highly scalable architecture for 8-wide-and-beyond cores, engineered for high-performance, throughput-oriented datacenter workloads.
- 8+ wide superscalar
- Server-class performance
- Highly scalable architecture
Inside HP-Secure 1.0
Multi-tenant by hardware
Conventional root-of-trust blocks serve one security context at a time. HP-Secure partitions into independent, hardware-isolated tenants — each with its own keys and sessions, each attachable to a separate virtual machine — so a single engine secures many workloads without ever crossing a trust boundary.
A broader, more modern algorithm suite
Beyond the classic standard set, HP-Secure includes the algorithms modern systems actually rely on — AES-XTS for storage, the SHA-2 and SHA-3 families, and ChaCha20-Poly1305 — in the same block.
Proven on silicon, not just simulated
The complete feature set runs today on a single low-cost FPGA, with every mode checked against its published standard answer on real hardware.
Verification you can stand behind
Every algorithm is validated bit-for-bit against an independent, FIPS-grade reference across tens of millions of randomized vectors — behavior, not a spec sheet.
Scales with your design
One engine spans a compact edge footprint to high-throughput data-plane configurations — sized to the system you're protecting, not the other way around.
Plug-and-play
A single engine-agnostic interface hides the cryptography: integrate once, and the core can be upgraded without touching your system.
Inside HP-Secure 3.0
Inline confidential compute for the fabric
Line-rate encryption, authentication, key management and compression for CXL/PCIe fabrics, memory expanders and data movers — all inline and streaming, so plaintext never lands in shared memory and key material stays protected on-chip.
Multi-tenant by construction
SR-IOV-style isolated session slots with hardware-enforced per-tenant keys that never cross — the confidential-compute story for multi-VM, multi-customer memory and fabric traffic that fixed parts don't expose.
A broad crypto + compression suite
Bulk ciphers (AES-CTR/XTS/CBC/ECB, ChaCha20), the full AEAD family (AES-GCM, AES-CCM, ChaCha20-Poly1305), hashing and MAC (SHA-2/3, HMAC, CMAC, HKDF), key-wrap, KDF and DRBG, plus inline LZ4 compression before encrypt — broader than the Structera baseline it matches.
One RTL, every SKU
Every feature is a compile-time capability bit — the config is the SKU. Dial area, width and feature set to your node and power budget, and replicate engines for concurrent line rate.
Licensable IP you own
A drop-in, synthesizable RTL block that integrates into your SoC or chiplet and ships under your part — the same inline confidential-compute as a fixed competitor part, but in silicon you control.
Verification you can license on
Anchored to OpenSSL across tens of millions of random vectors with zero mismatch, then the RTL is correlated bit-exact under randomized multi-tenant load — a package you can stand behind, not an assertion.
Inside HP-VPU (NPU)
Two engines on one substrate
A standards-compliant RISC-V Vector (RVV-1.0) processor and a dense INT8/INT4 GEMM engine for transformer inference, sharing one banked vector register file — a programmable ISA and weight-resident matmul in the same lane, not a fixed-function block with a proprietary ISA.
Built for the regime that decides real tokens/s
Token-by-token decode is memory-bound, where large arrays run at a fraction of their peak. HP-VPU keeps weights resident and folds INT4 weights with INT8 activations, sustaining high MAC-utilization on real transformer layers — so more of the nameplate becomes real work.
Scales by replication, no broadcast wall
The compute lane is vertical and tiles cleanly: add tiles and throughput scales linearly while critical-path depth stays constant. Size the engine to the throughput point you need without redesigning it.
Selected by configuration, not silicon
One config file sets datapath width, precision (INT8 or INT4), and which engines instantiate. One RTL, many PPA points — and you own and integrate the source, with new ops or activations added without a silicon respin.
Fully quantized, numerically stable
INT8 activations, INT4 weights, INT32 accumulate — with stable softmax and norms via LUT activations and no floating-point unit on the critical path. Composes attention, softmax, RMSNorm/LayerNorm, SwiGLU and GELU-MLP end-to-end, all integer.
Verified against open standards, proven on FPGA
Validated by a differential methodology: byte-exact, element-for-element against the official RISC-V reference (Spike) and a SystemC oracle, then RTL cross-checked against the model. A complete LLM forward-pass runs on a low-cost FPGA today — the whole datapath on real hardware, not just simulation.
Shipping product lines support FPGA deployment or licensable IP for ASICs at 2 GHz and above. The HP-Secure 1.0 and 3.0 engines are built on a multi-tenant, confidential-compute architecture.
Platform
The complete on-premise AI acceleration stack
From silicon to software, every layer of the ProsperaHub platform is designed for maximum performance, security, and operational simplicity.
Proprietary IP Core
Our custom-designed FPGA IP cores are optimized for AI inference workloads, delivering up to 10x performance improvement over general-purpose solutions.
Security
Security at every layer
Our defense-in-depth approach ensures your data and models are protected from silicon to application.
Deployment Architecture
Ready to deploy sovereign AI infrastructure?
Our team of engineers will work with you to design a custom on-premise deployment tailored to your security requirements, workload characteristics, and compliance obligations.
Typical deployment timeline: 4-8 weeks from initial consultation to production.